1. Field of the Invention
The present invention generally relates to the field of digital delay devices, digital oscillators including such delay devices and, more generally, clock signal generators which generally include at least one digital oscillator.
2. Description of the Relevant Art
There is known, from the article entitled “An all-Digital PLL Clock Multiplier” by Messrs Thomas Olsson and Peter Nilsson, ap-asik 2002, available at the address www.ap-asik.org/2002/Proceedings/5B 3.pdf, a digital phase locked loop produced in integrated technology on the basis of standard cells found in most libraries of standard digital cells. The phase locked loop has a frequency within the range 152 to 366 MHz and includes a looped structure with a phase detector, a filter, a digitally controlled oscillator and a frequency divider. The filter includes a counter and a recursive digital filter. For applications demanding a high resolution and a low consumption of the digitally controlled oscillator, a specific design is preferable. For high operating frequencies, a digital-to-analogue converter followed by a voltage-controlled oscillator may be a good alternative.
As known, digital systems on integrated circuits require clocks for timing their functioning. The clocks may be generated externally or internally using phase locked loops. Phase locked loops are digital or analogue and may be difficult to adjust and are relatively expensive. In fact, phase locked loop is a second order system similar to position locked loop using an error which is an acceleration. It may therefore produce instabilities in certain operating conditions.
In totally asynchronous communication systems for which maintaining phase consistency is not essential, it is possible to use a frequency locked loop whose design is simpler since only the frequency is guaranteed and not the phase with respect to the reference signal. A frequency locked loop is a first order system, similar to a speed locked loop on the basis of a measured speed error.
In other words, a phase locked loop and a frequency locked loop may be illustrated by a locked loop with a moving train. A phase locked loop amounts to choosing the start of a carriage of the train and in trying to always remain at the position of the start of the chosen carriage. Frequency locked loop is like a locked loop aiming to increase its speed or to reduce it by a fixed quantity as soon as there is a late or early carriage.
A possible implementation of a frequency locked loop uses a digitally controlled oscillator provided with programmable delays, each delay being commanded by a digital signal. Now, the precise control of delay times becomes more important as the frequency rises.